Recently, semiconductor devices have been designed to be highly integrated and operate at high speeds with a low driving voltage. In, for example, conventional metal oxide silicon field effect transistors (MOSFETs), high-speed operation of the semiconductor device requires a reduction in the length of the channel of the MOSFET. As the channel length of the MOSFET is reduced, an electric field caused by the drain voltage may negatively effect the channel region in the MOSFET and cause decreased reliability of the gate control due to the short channel effect. Furthermore, the reduction of the channel length may result in an increase of ion concentration in the channel region, and possibly cause a reduction of the carrier mobility in the channel region, thereby decreasing a driving current of the MOSFET. A leakage current may also be increased due to a decreased junction depth between a source region and a drain region of the MOSFET.
To address the problems with the MOSFETs discussed above, a silicon-on-insulator (SOI) substrate has been utilized for manufacturing semiconductor devices. An active region of the device is isolated from the SOI substrate. The SOI substrate typically includes bulk silicon. An insulating layer and an upper silicon layer are sequentially stacked on the substrate. A semiconductor device formed on the SOI substrate may provide a reduced junction capacitance and a driving current may be increased. However, the semiconductor device formed on the SOI substrate may also exhibit frequent variation of the threshold voltage due to non-uniformity of the upper silicon layer, a decrease of the driving current due to a self-heating effect caused by insulation from a lower portion of the substrate, and/or a floating channel effect.
To address the problems of semiconductor devices formed on the SOI substrate, buried oxide patterns may be formed under a surface of the substrate. This technique is discussed, for example, in U.S. Pat. No. 6,403,482 ('482), which discusses a transistor including the buried oxide pattern selectively formed under the source and drain contact regions. However, the process disclosed in the '482 patent exhibits a high contact resistance due to a reduction in a contact surface of the source and drain regions. Furthermore, a junction leakage current may not be efficiently prevented since the source and drain regions contact the well region.
Accordingly, a second method of addressing the problems discussed above with respect to semiconductor devices formed on SOI substrates has been proposed. In particular, the buried oxide pattern may be formed on an etched germanium layer. A silicon layer and a silicon germanium layer may be formed on the substrate using, for example, an epitaxial growth process, and the silicon germanium layer may be partially etched away. The buried oxide pattern is formed along the etched portion of the silicon germanium layer. However, the process using the epitaxial growth process typically requires a process change in subsequent processes. Furthermore, the epitaxial growth process may be costly, which may become a financial burden if the semiconductor device were to be mass produced. Accordingly, improved semiconductor devices providing decreased junction leakage currents and junction capacitances with a competitive manufacturing cost may be desired.